The present invention relates to a dynamic RAM (Random Access Memory) device and to the technology useful for fabricating a semiconductor memory with a storage capacity as large as 4 mega-bits.
Advanced semiconductor technology has enabled the development of a dynamic RAM as capacious as 1 megabits. RAM chips with such an increased storage capacity imposes an extended time period for testing. To cope with this matter, there is known a dynamic RAM chip which is provided therein with a test circuit, and is conducted in such a way wherein the same signal is written in different storage locations, each being a multiple of 4 bits, in the memory array and, if any one bit out of the signal retrieved from the memory array is inconsistent, the output terminal is brought to a high-impedance state. In the case where all bits of the read-out signal are high or low, the output terminal is enabled to output a high-level or low-level signal. (For details refer to the publication entitled "Mitsubishi Giho", Vol. 59, No. 9, published in 1985 by Mitsubishi Electric Corp.)
In the above test scheme, an unused pin on the 18-pin package is used to bring the RAM chip from the normal operating mode into the test mode in which the test circuit is activated. However, if a capacious dynamic RAM chip, e.g., a 4M bit RAM, is intended to be fabricated in conjunction with an 18-bit package, it uses up all spare pins to receive the address signal, and therefore the above-mentioned testing cannot be implemented.